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Giovanni DeMicheli

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Stand Alone

High Level Synthesis of ASICs under Timing and Synchronization Constraints
High Level Synthesis of ASICs under Timing and Synchronization Constraints (The Springer International Series in Engineering and Computer Science, 177)
Hardware/Software Co-Design
Hardware/Software Co-Design
Design systems for VLSI circuits logic synthesis and silicon compilation ; [proceedings of the NATO Advanced Study Inst. on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7 - 18, 1986]